The present invention relates to semiconductor devices and methods of forming the same, and more particularly, to a contact structure in semiconductor devices and methods of forming the same.
As semiconductor devices become more highly integrated, it is generally more difficult to ensure stable operations of transistors therein. A recess channel array transistor (RCAT) has been introduced as a transistor structure addressed to improving problems, such as a short channel effect, while reducing the size of a transistor.
In the RCAT, a gate electrode is typically positioned to protrude upward from a semiconductor substrate. As a result, it may be difficult to perform subsequent processes, such as a contact plug formation process and a planarization process, due to the protruded gate electrode. An upper corner of a recessed channel region may cause the generation of a leakage current due to a field crowding effect. Also, a difficult patterning process is typically required to form the protruded gate electrode.
Studies on a buried channel array transistor (BCAT) have been conducted to address the aforementioned problems. For example, a semiconductor device having buried word lines is disclosed in U.S. Pat. No. 6,770,535(B2), entitled “Semiconductor integrated circuit device and process for manufacturing the same” to Yamada, et al.
In the BCAT, a gate electrode is typically buried in a semiconductor substrate. A capping pattern is formed on the buried gate electrode. The capping pattern is generally formed to have the same level as a top surface of the semiconductor substrate. That is, the buried gate electrode is formed to have a lower level than the top surface of the semiconductor substrate due to the capping pattern. Source/drain regions are generally formed in the semiconductor substrate on both sides of the buried gate electrode.
Semiconductor devices, such as dynamic random access memories (DRAMs), may include a plurality of BCATs. These semiconductor devices typically include interconnections between components thereof, such as bit lines and capacitor electrodes that act as storage nodes. For example, a semiconductor substrate having the BCAT is typically covered by a lower interlayer dielectric layer. The bit lines are generally arranged on the lower interlayer dielectric layer. The bit line generally is connected to a selected one of a plurality of source/drain regions through a direct contact plug. The direct contact plug may be formed in a contact hole extending through the lower interlayer dielectric layer.
An upper interlayer dielectric layer is generally formed that covers the bit lines. Buried contact plugs may be formed to sequentially pass through the upper and lower interlayer dielectric layers and then contact the source/drain regions at both sides of the bit lines. Storage nodes may be formed on the buried contact plugs.
BCATs generally have a reduced structure as compared with the RCATs. As such, methods of forming a contact plug used for RCATs may not be directly applied to BCATs. In particular, a patterning process having a relatively high degree of difficulty may be needed for forming contact holes in BCATs. The more difficult patterning process may cause degradation of production efficiency and an increase of manufacturing costs for the BCATs.